Bring up and debug the twosigma/frost RV32GCB SystemVerilog CPU (an out-of-order, Tomasulo-style core): the…
Bring up and debug the twosigma/frost RV32GCB SystemVerilog CPU (an out-of-order, Tomasulo-style core): the…: a task in Long-Horizon Terminal-Bench (LHTB) (Harbor dataset). You are the verification engineer bringing up the frost RV32GCB RISC-V core (an out-of-order, Tomasulo-style superscalar…
The task
You are the verification engineer bringing up the **frost** RV32GCB RISC-V core (an out-of-order, Tomasulo-style superscalar implementation). The RTL under `hw/rtl/` has been seeded with an **unknown number of deliberately-injected bugs**. They are spread across the design — some in the datapath (ALU, shifter,…